Wire-bonded through-silicon vias with low capacitive substrate coupling
نویسندگان
چکیده
منابع مشابه
Test Planning for 3D Stacked ICs with Through-Silicon Vias
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorit...
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ژورنال
عنوان ژورنال: Journal of Micromechanics and Microengineering
سال: 2011
ISSN: 0960-1317,1361-6439
DOI: 10.1088/0960-1317/21/8/085035